Method and system for resource sharing between demodulating paths of a rake receiver

ABSTRACT

A rake receiver for high data rate communications systems is provided that is able to share resources between demodulating branches without using independent hardware resources for each finger. The rake receiver of the present invention uses less circuitry while keeping functional equivalence, and it requires relatively smaller additional area when increasing the number of demodulating branches, thereby having a significantly smaller size, being able to track more demodulating paths for increasing performance, and being less complex as compared to conventional rake receivers for high data rate communications systems.

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field

[0002] The present disclosure relates generally to mobilecommunications, and more particularly, to a method and system forresource sharing between demodulating paths of a rake receiver. Ingeneral, a rake receiver combines signals that are transmitted on achannel in different paths from a transmitter and arrive at differenttime points in order to increase reception performance through pathdiversity.

[0003] 2. Background of the Related Art

[0004] As shown in FIGS. 1 and 2, a conventional rake receiver 100includes an RF analog subsystem block 102, which converts signalsreceived from an antenna 104 to digital data and feeds the converteddigital data to each finger 106 ₁-106 _(N). In each finger 106 ₁-106_(N), symbols transmitted from the transmitter are demodulated by PNdespreading blocks 108 ₁-108 _(N).

[0005] The demodulated symbols Wi and the estimated pilot channel gainsPi are provided by Walsh decovering blocks 110 ₁-110 _(N) and pilotfilter blocks 111 ₁-111 _(N), and they are transferred to channelestimation and phase distortion compensation blocks 112 ₁-112 _(N). Therecovered symbols Si are stored in a kind of FIFO memory within timedeskew buffers 114 ₁-114 _(N) respectively. A symbol combiner 116 readsthe symbols from the time deskew buffers 114 ₁-114 _(N) (four timedeskew buffers are shown in FIG. 2) of the fingers at the same time,combines them, and sends the symbols to a long code descrambler 118 forcombining the symbols with a long code. A power-bit extractor 120 isconnected to each time deskew buffer 114 ₁-114 _(N) and to the symbolcombiner 116.

[0006] In FIG. 2, reference characters A, B, C and D denote symbol datastored in time deskew buffers 114 ₁, 114 ₂, 114 ₃, and 114 _(N) of therake receiver 100. The symbols are numbered to represent their sequencenumbers. The pluralities of demodulating fingers 106 ₁-106 _(N) operatein the same manner to demodulate signals with different arrival times.Therefore, the hardware of each finger 106 ₁-106 _(N) has the samestructure.

[0007] Each demodulating finger 106 ₁-106 _(N) in the rake receiver 100demodulates the symbols independently in a temporal sense, and storesthe demodulated symbols in the time deskew buffers 114 ₁-114 _(N). Thatis, since symbol combination can be performed by the symbol combiner 116only after demodulation of the symbols of each finger 106 ₁-106 _(N),the time deskew buffers 114 ₁-114 _(N) store previously demodulatedsymbols until a symbol from the last branch is demodulated. Finally, allthe symbols stored in the time deskew buffers 114 ₁-114 _(N) arecombined in the symbol combiner 116. In order to enable each finger tooperate in its own timing reference, an independent time deskew bufferwith the same size as the time deskew buffers 114 ₁-114 _(N) is providedfor each finger 106 ₁-106 _(N).

[0008] For example, the required size of a time deskew buffer for one ofRC3, 4 and 5 modes of a CDMA2000 system is(FCH_FIFO_DEPTH+SCH_FIFO_DEPTH+DCCH_FIFO_DEPTH+PILOT_ENERGY_FIFO_DEPTH)×DATA_WIDTH×numberof fingers. Thus, the depth of the FIFO memory for storing data isincreased and the architecture or structure of the rake receiver forthird high data rate communications systems becomes complex.

[0009] In third generation systems, such as CDMA2000 and UMTS, or otherhigh data rate communications systems, the required depths of the FIFOsare remarkably increased since more symbols are to be stored for higherdata rate. In addition, the number of fingers is increased since morefingers are necessary to facilitate soft hand-offs and enhancemulti-path diversity effects. The fact that an independent time deskewbuffer of the same size as the time deskew buffers 114 ₁-114 _(N) mustbe provided for each finger 106 ₁-106 _(N), thereby causes an increasein the size of the FIFO memory, or time deskew buffers 114 ₁-114 _(N),in proportion to the number of fingers 106 ₁-106 _(N). Hence, there isan increase in the size and complexity of the rake receiver.

[0010] Accordingly, a need exists for a rake receiver for high data ratecommunications systems that is able to share resources betweendemodulating branches without using independent hardware resources,i.e., such as an independent time deskew buffer of the same size as thetime deskew buffers 114 ₁-114 _(N) for each finger 106 ₁-106 _(N), tothereby reduce the area and complexity of the rake receiver.

SUMMARY OF THE INVENTION

[0011] The present invention provides a rake receiver for high data ratecommunications systems that is able to share resources betweendemodulating branches without using independent hardware resources foreach finger. That is, the rake receiver of the present invention usesless circuitry while increasing the number of demodulating branches,thereby having a significantly smaller size, being able to track moredemodulating paths for increasing performance, and being less complex ascompared to conventional rake receivers for high data ratecommunications systems.

[0012] The rake receiver of a first embodiment according to the presentinvention includes a plurality of demodulating paths for demodulatingsymbols, a memory storage block for storing corresponding demodulatedsymbols from each of the plurality of demodulating paths; and storagecontrol circuitry connected to each of the plurality of demodulatingpaths for receiving the demodulated symbols and for controlling thestorage of the demodulated symbols within the memory storage block.

[0013] The rake receiver of a second embodiment according to the presentinvention includes a plurality of demodulating paths for demodulatingsymbols; storage control circuitry connected to each of the plurality ofdemodulating paths for receiving the demodulated symbols; a phasecompensator connected to the storage control circuitry for receiving thedemodulated symbols corresponding to each of the plurality ofdemodulating paths and for phase-compensating the demodulated symbols;and a memory storage block for receiving the phase compensated,demodulated symbols corresponding to each of the plurality ofdemodulating paths and for storing the demodulated symbols in accordanceto signals received from the storage control circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The invention is farther explained by way of example and withreference to the accompanying drawings, wherein:

[0015]FIG. 1 is block diagram of a prior art rake receiver;

[0016]FIG. 2 is a diagram illustrating symbol combining timing in theprior art rake receiver shown by FIG. 1;

[0017]FIG. 3 is a block diagram of a rake receiver having a time deskewbuffer sharing architecture according to a first embodiment of thepresent invention;

[0018]FIG. 4 is a diagram illustrating symbol combining timing whensharing the time deskew buffer sharing structure shown by FIG. 3;

[0019]FIG. 5 is a block diagram of a rake receiver having a time deskewbuffer and phase compensator sharing architecture according to a secondembodiment of the present invention;

[0020]FIG. 6 is a block diagram of a priority decision logic block foruse in the time deskew buffer and phase compensator sharing architectureaccording to the present invention;

[0021]FIG. 7 is a logic block diagram of a pending status state machineblock of the priority decision logic block of FIG. 6;

[0022]FIG. 8 is a diagram illustrating operation of the pending statusstate machine block of the priority decision logic block of FIG. 6;

[0023]FIG. 9 is a diagram illustrating operation of the resource sharingstate machine block of the priority decision logic block of FIG. 6;

[0024]FIG. 10 is a logic block diagram of an acknowledgement signalgeneration logic block of the priority decision logic block of FIG. 6;

[0025]FIG. 11 illustrates timing diagrams for the first embodiment ofthe rake receiver architecture as shown by FIG. 3;

[0026]FIG. 12 illustrates timing diagrams for the second embodiment ofthe rake receiver architecture as shown by FIG. 5;

[0027] FIGS. 13A-C illustrate temporal representations offinger/searcher positions;

[0028]FIG. 14 is a schematic diagram of a two-finger positioncomparator;

[0029]FIG. 15 is a schematic diagram of a four-finger positioncomparator; and

[0030]FIG. 16 is a logic diagram of earliest finger decision logiccircuitry.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0031] The present invention provides a rake receiver for high data ratecommunications systems that is able to share resources betweendemodulating branches without using independent hardware resources foreach finger. That is, the rake receiver of the present invention usesless circuitry while increasing the number of demodulating branches,thereby having a significantly smaller size, being able to track morepaths for increasing performance, and being less complex as compared toconventional rake receivers for high data rate communications systems.

[0032] In a first embodiment of the inventive rake receiver sharingstructure, time deskew buffers are shared between demodulating branches.In a second embodiment of the inventive rake receiver sharing structure,time deskew buffers and a phase compensator are shared betweendemodulating branches. In the first embodiment, the memory area requiredto implement the FIFO is decreased to approximately 1/(number ofdemodulating branches) as compared to a typical prior art rake receiver;for example, the rake receiver shown by FIG. 1. While in the secondembodiment, the size of the inventive rake receiver is furtherdecreased, because the logic area required to implement the phasecompensator is decreased to 1/(number of demodulating branches) and amemory controller used for controlling sharing of the time deskewbuffers is also used for controlling sharing of the phase compensator.

[0033] First Embodiment

[0034] With reference to FIG. 3, there is shown a rake receiveraccording to the first embodiment designated generally by referencenumeral 300. The rake receiver 300 includes an RF analog subsystem block302, which converts signals received from an antenna 304 to digital dataand feeds the converted digital data to each finger 306 ₁-306 _(N). Ineach finger 306 ₁-306 _(N), symbols transmitted from the transmitter aredespreaded by PN despreading blocks 308 ₁-308 _(N).

[0035] The demodulated symbols Wi and the estimated pilot channel gainsPi are provided by Walsh decovering blocks 310 ₁-310 _(N) and pilotfilter blocks 311 ₁-311 _(N) respectively, and they are transferred tophase compensation blocks 312 ₁-312 _(N). Therefore, the final output ofeach demodulating finger 306 ₁-306 _(N) is phase-compensated symboldata. The symbol data belong to different physical channels and the datarate of each channel is variable according to circumstances. In thephysical channels, each channel is identified by corresponding Walshcode or OVSF code on a radio link. Here, a CDMA2000 system is providedas an example.

[0036] The types and number of physical channels vary according to RC(Radio Configuration) in the CDMA2000 system. If RC is one of 3, 4 and5, the physical channels are an FCH (Fundamental Channel) fortransmission of a voice signal, an SCH (Supplemental Channel) fortransmission of data, a DCCH (Dedicated Control Channel) fortransmission of a control signal, Pilot Channel Energy for forward powercontrol, and Power Control Subchannels 1, 2 and 3 for reverse powercontrol. If RC is one of 1 and 2, the physical channels are FCH, SCHs 1to 7, and Power Control Subchannels 1, 2, and 3.

[0037] The phase-compensated symbols Si outputted by the phasecompensation blocks 312 ₁-312 _(N) are also transmitted to and stored ina common time deskew buffer block 314 (Single Memory for N branches of Mchannel paths). The symbols Si are transmitted to the common time deskewbuffer block 314 via operand selection logic block 316 and a symbolcombiner 318. Accordingly, demodulated symbols corresponding to eachfinger 306 ₁-306 _(N) are stored in the common time deskew buffer block314. That is, the common time deskew buffer block 314 is shared by allthe fingers 306 ₁-306 _(N).

[0038] Since the common time deskew buffer block 314 is supposed to beimplemented with a single-port memory for the best area efficiency, onlyone read or write operation can be performed at a particular time.Accordingly, the operand selection logic block 316 of the rake receiver300 does not allow two or more data write requests entailing writingdata to the buffer block 314 to be performed at the same time. Thus,when a write request signal in each channel of each branch is generated,the corresponding symbol is not stored immediately. Instead, it issuspended until the write request is acknowledged. In the same manner, aread request is suspended until it is acknowledged. Since the timing ofeach finger and a combiner is independent with one another, two or morewrite or read requests can occur at the same time. There is a need forarbitration to appropriately select one of the write or read requests todetermine which one to process first.

[0039] For this purpose, priority decision logic block 600 is providedfor determining the signal of the highest priority among the write orread requests that are pending, and the operands from the selectedrequest are handled by the operand selection logic block 316. A detaileddescription of the functions and operation of the priority decisionlogic block 600 is provided below with reference to FIGS. 6-10. A memorycontroller 326 determines which actions to take according to the type ofoperation, which is read or write, of the selected request. When theselected request is a write operation, the memory controller 326 furtherdetermines whether to directly store the symbol selected by the operandselection logic block 316 into the common time deskew buffer block 314or to combine it with the symbol stored in the common time deskew bufferblock 314 using the symbol combiner 318. The direct storage is chosenwhen the processed symbol is from the earliest demodulating path.Otherwise, the symbol combining with the stored symbol is chosen. Foreach of M channels, N symbols received by the N demodulating fingers areadded in the order of receipt into the corresponding position in thecommon time deskew buffer block 314. This is described in more detailbelow.

[0040] After the symbols received by the N demodulating fingers arecombined to generate a single result, the symbol combiner 318 reads thecombined symbol from the common time deskew buffer block 314 (foursymbol sequences corresponding to four fingers of the rake receiver 300and the status of the memory contents within the common time deskewbuffer block 314 where the 3 ^(rd) symbols corresponding to each fingerare stored are shown in FIG. 4), and sends the combined symbol to a longcode descrambler 320 for descrambling the symbol with a long code. Thecombined symbols are also sent to a power-bit extractor 322 forextracting the power bits.

[0041] In FIG. 4, with an assumption that the number of fingers N is 4,reference characters A, B, C and D denote symbol data corresponding tofingers 306 ₁, 306 ₂, 306 ₃, and 306 _(N), respectively. The symbols arenumbered to represent their sequence numbers. The pluralities ofdemodulating fingers 306 ₁-306 _(N) operate in the same manner todemodulate signals with different arrival times. The hardware of eachfinger 306 ₁-306 _(N) has the same structure.

[0042] Symbols with same number are stored at the same position of thememory 314. In FIG. 4, memory contents for symbol #3 are shown, as anexample. Upon receipt of a symbol A3 (A3 is the earliest received symbolfrom the series of demodulated symbols A3 to D3), it is written at apredetermined position of the memory 314 directly. Then, when a symbolB3 (B3 is the next symbol) is received, the symbol A3 is read from thememory 314, combined to the symbol B3, and re-written at the sameposition of the memory 314. Symbols C3 and D3 are also combined with theprevious symbols in the same manner. Hence, after the symbol D3 isreceived, the value stored in the memory 314 is A3+B3+C3+D3.Accordingly, the Symbol Combiner 318 reads the value at a correspondingposition of the memory 314, that is, A3+B3+C3+D3.

[0043] For the rake receiver 300, each branch demodulator, or finger 306₁-306 _(N), transmits a write request signal to the memory controller326 for sharing resources, before storing phase-compensated symbols inthe common time deskew buffer 314. For example, if RC in the CDMA2000system is one of 3, 4 and 5 and the CDMA2000 system has four fingers,seven physical channels exist for each finger. Therefore, write requestsare generated with variable timing from a total of 28 physical channels.On the other hand, read requests are generated with variable timing froma total of 7 physical channels. The priority decision logic block 600senses each request from the fingers and the combiner, and the requestsare serviced one-by-one according to priority.

[0044] That is, since the rake receiver 300 includes only one commonmemory 314 (Single Memory for N branches of M paths), a write requestfor a symbol from the earliest demodulating path is written in apredetermined area of the time deskew buffer 314. Then, other writerequests for symbols from the succeeding demodulating paths are servicedby combining the symbol with the previously stored symbol, and thecombined symbols are stored in the same area of the time deskew buffer314. This operation is repeatedly performed until a write request for asymbol from the last demodulating path is completely processed.Therefore, when symbol combining of the last demodulating path iscompleted, the symbols from all paths have been properly combined andstored in a specific area of the common time deskew buffer 314.

[0045] Hence, it first must be determined before writing a presentsymbol in the time deskew buffer 314 of the resource sharing rakereceiver structure 300 according to the present invention, whether thepresent symbol belongs to the earliest demodulating path or finger. Thedetermination is made by comparing the positions of the fingers in theembodiment of the present invention. The position of a particular fingerrefers to a timing difference of the PN sequence generator of thesearcher and each finger from the initial value “0”.

[0046] The PN sequence generators of the searcher and each finger areinitiatialized to “0” at an arbitrary time in order to detect therelative temporal difference between the PN sequence generator of thesearcher and a corresponding finger of the rake receiver 300. In theCDMA2000 system, the position range is the period of a short PNsequence, approximately 26.67 ms, i.e., 32768 PN chips, and theresolution is ⅛ chip. Therefore 18 bits are used to represent theposition of a finger or searcher.

[0047] For ease of explanation, assume that there is an imaginary PNgenerator that runs regularly after initialization. The operation inwhich the PN sequence generator of a finger or a searcher runs faster orslower than the imaginary PN generator is called slew operation. Therelative temporal difference of slewed fingers is shown by FIGS. 13A-C.Since the period of short PN code is 32768 chips, the positions of PNgenerators can be represented in a circle. The imaginary PN generator isnever slewed, thus its position is fixed at 0. The position of a PNgenerator running slower than the imaginary PN generator is plotted withpositive angle in clockwise sense in FIGS. 13A and 13C. On the otherhand, the position of a PN generator running faster than the imaginaryPN generator is plotted with negative angle in clockwise sense in FIGS.13B and 13C. Comparing the positions of two fingers can be accomplishedby subtracting the position of a finger from that of the other one.

[0048] If two or more fingers are at the same position, then todetermine the earliest finger, or demodulating path, the fingers arenumbered with 00(bin), 01(bin), 10(bin) and 11(bin) to the 18-bitpositions of ⅛ PN chip units. Therefore, the relative sequence of eachfinger can be determined by subtraction between 20-bit positions.

[0049] Circuitry which compares the positions of two fingers is shown byFIG. 14. Two 20-bit positions, P0 and P1, are formed by concatenating18-bit positions of finger 0 and 1 with their corresponding tail bits00(bin) and 01(bin). When P1 is subtracted from P0, the MSB (MostSignificant Bit) of the 20-bit result, P0_LE_P1, designates whichposition is earlier than the other. If P0 is 0 degrees to positive 180degrees apart from P1, P0_LE_P1 becomes 0, which means finger 1 isearlier than finger 0. If P0 is 0 degrees to negative 180 degrees apartfrom P1, P0_LE_P1 becomes 1, which means finger 0 is earlier than finger1. It is ambiguous to determine an earlier one when two fingers are 180degrees apart, but such situation is impossible since there is aphysical time limit between the arrival of multipath components, whichmeans the fingers are never deployed far from one another.

[0050] Extending the function of the two-finger position comparator inFIG. 14, the earliest finger can be determined by comparing each fingerpair after comparing finger pairs independently, if four fingers aregiven. A circuitry to compare the positions of 4 fingers is shown byFIG. 15. In the four finger comparators, earlier of P0 and P1 aredetermined using the subtractor 1501 and the MSB selector 1502. Andthen, the earlier of the two positions, represented as PA, is selectedwith the multiplexer 1503 using the result P0_LE_P1. In the same manner,the earlier one of P2 and P3, represented as PB, is also selected usingthe subtractor 1504, the MSB selector 1505, and the multiplexer 1506.Finally, whether PA is earlier than PB or vice versa is determined usingthe subtractor 1507 and the MSB selector 1508. Inspecting PA_LE_PB,P0_LE_P1, and P2_LE_P3 reveals which finger is the earliest one byapplying a simple rule. If PA_LE_PB is 1, either P0 or P1 is theearliest, the earliest of which is further determined by P0_LE_P1. IfPA_LE_PB is 0, either P2 or P3 is the earliest, the earliest of which isfurther determined by P2_LE_P3.

[0051] Circuitry which does this decision is shown by FIG. 16. Only oneof the four outputs of the circuit is 1, and the output with value 1designates the earliest finger. Accordingly, when a write request isgenerated, the memory controller 326 determines whether to writedirectly a symbol to the common time deskew buffer 314, or to combinethe symbol with a previous symbol and then write the combined symbol tothe common time deskew buffer 314 according to whether the finger whichgenerated the write request is the earliest one.

[0052] Since corresponding signals from all demodulating paths arecombined and stored at the same position or area of the memory 314, thecapacity requirement of the memory 314 is significantly reduced. Forexample, the size of a deskew buffer required at one of the RC3, 4 and 5modes in the CDMA2000 system using the inventive rake receiver 300 is(FCH_FIFO_DEPTH+SCH_FIFO_DEPTH+DCCH_FIFO_DEPTH+PILOT_ENERGY_FIFO_DEPTH+PWR_SUBCHANNEL_DEPTH×3)×(DATA_WIDTH+GUARD_BIT_WIDTH).

[0053] GUARD_BIT_WIDTH is log ₂(number of fingers) parameter used tostore a carry generated during symbol combining. Though this guard bitmakes the memory required for the resource sharing structure larger thanthe memory required for one finger of a prior art, the increased memorycapacity requirement is negligible. Further, the memory requirement isreduced by 75% in a four-finger system using the inventive rake receiversharing structure 300.

[0054] Additionally, since PWR_SUBCHANNEL_DEPTH, a space necessary toseparately store power control symbols for each cell and combine them,as described below, is much smaller than SCH_FIFO_DEPTH used inconventional rake receivers, its contribution to the memory capacityrequirement increase is also negligible. Also, in the inventive rakereceiver 300, at the RC1 or 2 modes, up to seven SCCHs are used insteadof a single SCH used at the RC3, RC4, or RC5 modes. The portion ofmemory used for SCH is large enough to accommodate seven SCCHs.Accordingly, the memory capacity for the SCH is evenly divided andassigned to SCCH #1 to #7 without the need of additional memory capacityat the RC1 or 2 modes.

[0055] While conventional rake receiver structures combine the symbolsbelonging to different physical channels in parallel according to thecorresponding symbol boundary generated by an internal RTG (ReferenceTiming Generator), the resource sharing rake receiver structure 300according to the first embodiment of the present invention transmits aread request to the memory controller 326 according to the RTG timing.That is, if RC is 3, 4, or 5, read requests are generated with variabletiming from seven physical channels and the memory controller 326processes each read request from the physical channels one-by-oneaccording to a priority scheme. The write requests are processed in thesame manner by the memory controller 326. Accordingly, even if a writerequest and a read request are generated simultaneously, one of therequests is processed first according to the priority scheme. That is,the time deskew memory 314 is not implemented with a dual port memorythat enables simultaneous writing and reading, but with a single portmemory.

[0056] Symbol combining will now be described in the case of powercontrol symbols. While symbols from all paths are simply summed forsymbol combining by the inventive rake receiver 300, power controlsymbols are grouped according to corresponding cells before they arecombined.

[0057] In a conventional rake receiver, it is possible to distinguishwhich cell a certain symbol is transmitted from after the deskewoperation, because symbols from individual paths are separately storedin the corresponding deskewer. But since all symbols are combined in thewriting step in the resource sharing rake receiver structure 300 of thepresent invention, power control symbols belonging to each cell areconsidered separately from the other symbols. In other words, a separatephysical channel is required for storing the power control symbols ofeach cell. In an exemplary embodiment of the present invention, threecells are supported and PWR_SUBCHANNELs 1, 2 and 3 separately combinesymbols belonging to cells #1, 2 and 3.

[0058] Second Embodiment

[0059] With reference to FIG. 5, there is shown a rake receiverstructure according to the second embodiment designated generally byreference numeral 500. The rake receiver structure 500 includes the RFanalog subsystem block 302, which converts signals received from theantenna 304 to digital data and feeds the converted digital data to eachfinger 306 ₁-306 _(N). In each finger 306 ₁ 306 _(N), symbolstransmitted from the transmitter are despreaded by the PN despreadingblocks 308 ₁-308 _(N). The demodulated symbols Wi and the estimatedpilot channel gains Pi are provided by Walsh decovering blocks 310 ₁-310_(N) and pilot filter blocks 311 ₁-311 _(N), and they are transferred tothe operand selection logic block 316. The output of each finger 306₁-306 _(N) is not a symbol but a correlator output for each channel andan estimated pilot channel gain.

[0060] In the same manner as for the case of sharing only the timedeskew buffer 314 of the first embodiment, the priority decision logicblock 600 selects one of the requests that have not been processed andreceives an operand corresponding to the selected request. A phasecompensator 502 multiplies a correlator output selected by the operandselection logic block 316 by the complex conjugate of the channelestimation value for performing phase compensation. That is, the phasecompensator 502 multiplies the output of the correlator for the selectedchannel in the selected finger by the output of a Pilot Filter (channelestimator filter) in the selected finger.

[0061] The memory controller 326 determines whether to write a currentsymbol directly in the memory 314 or to combine the current symbol withthe previously stored symbol before writing in the memory 314 accordingto whether the present write request belongs to the earliestdemodulating path, similar to the case of sharing only the time deskewbuffer 314 as in the first embodiment. That is, each finger 306 ₁-306_(N) transmits a write request signal to the priority decision logic 600after correlation. Upon receiving the write request signal, the prioritydecision logic 600 reads the previously stored symbol from the timedeskew buffer 314 and controls the phase compensator 502 to performcomplex multiplication of the current symbol. Then, the memorycontroller 326 combines the read symbol with the complex multiplicationresult and stores the combined result at the same position of the commontime deskew buffer 314.

[0062] The phase compensator 502 (or complex multiplier) includes twoMAC (Multiply and Accumulate) units. In this case, two clocks are takenfor complex multiplication. In addition, two clocks are also taken toread a symbol from the memory 314, combining it with another symbol, andstoring the combining result within the memory 314. These two steps arepipelined so that only two clocks are taken to process a write or readrequest as in the first embodiment.

[0063]FIG. 6 illustrates the overall structure of the priority decisionlogic block 600 for use in the resource sharing rake receiver structure300 and 500. Write requests for each physical channel transmitted fromthe corresponding fingers 306 ₁-306 _(N) and read requests for eachphysical channel transmitted from a FIFO read pointer of the RTG(Reference Timing Generator) 602 are registered in a pending statusstate machine 700. Here, request registration means transition of acorresponding WrPend (write pending) bit to 1 in case of a write requestand transition of a corresponding RdPend (read pending) bit to 1 in caseof a read request. Each write or read pending bit indicates that thecorresponding write or read request was generated but has not yet beenprocessed.

[0064] A channel priority decision logic block 604 and a finger prioritydecision logic block 606 select a channel and a finger, respectively, tobe processed according to priority among the presently pending requestsWrPend (write pending request) or RdPend (read pending request).Information about the selected channel and finger is fed to a resourcesharing state machine block 900 for controlling the memory controller326. The resource sharing state machine block 900 sends signals StCh(state channel), StRd (state read), and StFng (state finger) to thememory controller 326 and to an acknowledgment signal generation logicblock 1000 which generates an acknowledge signal WrAck (writeacknowledgment) or RdAck (read acknowledgment) for the processedrequest, transmits the acknowledge signal to the pending status statemachine block 700 to notify that the corresponding request was processedcompletely, and also to FIFO write/read pointer controller blocks 610,612 to increase the corresponding pointer value.

[0065]FIGS. 7 and 8 illustrate the structure and operation of thepending status state machine 700. In FIG. 7, the upper circuit is awrite request processing circuit for a K^(th) channel in a J^(th)finger, and the lower circuit is a read request processing circuit for aK^(th) channel in a J^(th) finger.

[0066] When a write or read request is generated, the pending statusstate machine 700 changes a flip flop state of flip flop 702 or 704 into1, notifying that a corresponding (write or read) request has beenregistered. When the process of the corresponding request (write orread) is completed, an acknowledge signal for the above request isgenerated and the flip flop state returns to 0. That is, once the flipflop state 1 is entered, the state is maintained until theacknowledgement signal is received for the corresponding request.

[0067] More particularly, the channel priority decision logic block 604determines the sequence (i.e., order) of the channels to be processedamong the pending bits of the state 1 according to a priority scheme,and outputs the selection result as a signal PrioCh (priority channel).The signal PrioCh selects a signal vector of the corresponding channelamong signals WrPend using a multiplexer 614. The multiplexer 614outputs a signal WrPendSel (write pending selection) for thecorresponding channel.

[0068] Table 1 lists physical channel assignments in the CDMA2000system, as an example. In the embodiment of the present invention, theSCH having the highest data rate is processed first by granting thehighest priority to it. Otherwise, it is possible that the previoussymbol is not completely processed until a new request for the next SCHsymbol is received, which means the symbol combing cannot be properlyperformed. TABLE 1 Physical channel assignments in the CDMA2000 system.Channel Number Physical Channel 1 FCH 2 SCH or SCCH1 3 DCCH 4 PilotEnergy 5 SCCH2, SCCH3 6 SCCH4, SCCH5 7 SCCH6, SCCH7 8 Power Subchannel 19 Power Subchannel 2 10  Power subchannel 3

[0069] Symbols in each physical channel are complex, which means theyare in the separated format in an I arm and a Q arm, but they should bemultiplexed into one stream, and thus a symbol reading logic has anarrower timing margin than a symbol generating logic (i.e., readinglogic has less idle time than writing logic). Hence, a higher priorityis given to a read request than a write request as shown in Table 2. Bythe same manner, as most write requests are processed within the symbolperiods of the channels; the SCH is processed with the highest prioritybecause it has the shortest symbol period for SF (Spreading Factor) 4.TABLE 2 An example of priority for channel selection Output Channel Name& Access Priority Input Condition PrioCh[10:1] PrioRd Type 1 Ch.2 RdPend= 1 ′b0000000010 1 SCH read 2 Ch.2 ′b0000000010 0 SCH write WrPend[N:1]! = 1 3 Ch.1 RdPend = 1 ′b0000000001 1 FCH Read 4 Ch.3 RdPend = 1′b0000000100 1 DCCH Read 5 Ch.4 RdPend = 1 ′b0000001000 1 SCCH2, SCCH3Read 6 Ch.5 RdPend = 1 ′b0000010000 1 SCCH4, SCCH5 Read 7 Ch.6 RdPend =1 ′b0000100000 1 SCCH6, SCCH7 Read 8 Ch.7 RdPend = 1 ′b0001000000 1Power Subchannel 1 Read 9 Ch.8 RdPend = 1 ′b0010000000 1 PowerSubchannel 2 Read 10 Ch.9 RdPend = 1 ′b0100000000 1 Power Subchannel 3Read 11 Ch.10 RdPend = 1 ′b1000000000 1 Pilot Energy Read 12 Ch.1′b0000000001 0 FCH write WrPend[N:1] ! = 1 13 Ch.3 ′b0000000100 0 DCCHwrite WrPend[N:1] ! = 1 14 Ch.4 ′b0000001000 0 SCCH2, SCCH3 WriteWrPend[N:1] ! = 1 15 Ch.5 ′b0000010000 0 SCCH3, SCCH3 Write WrPend[N:1]! = 1 16 Ch.6 ′b0000100000 0 SCCH4, SCCH3 Write WrPend[N:1] ! = 1 17Ch.7 ′b0001000000 0 Power Subchannel 1 Write WrPend[N:1] ! = 1 18 Ch.8′b0010000000 0 Power Subchannel 2 Write WrPend[N:1] ! = 1 19 Ch.9′b0100000000 0 Power Subchannel 3 Write WrPend[N:1] ! = 1 20 Ch.10′b1000000000 0 Pilot Energy Write WrPend[N:1] ! = 1

[0070] In case write requests belonging to the same physical channelsare generated simultaneously from two or more fingers, the fingerpriority decision logic block 606 can process the write requests in anarbitrary order because of the same timing margin in all fingers 306₁-306 _(N). Table 3 shows an example of finger priority where fingers306 ₁-306 _(N) with lower numbers are processed first and “X” indicates“don't care”. That is, Table 3 shows an example of priority decisionwhen write requests for the same channel are generated simultaneouslyfrom the plurality of fingers 306 ₁-306 _(N). TABLE 3 An example ofpriority for finger selection. WrPendSel[4:1] PrioFng[4:1] ′bXXX1 ′b0001′bXX10 ′b0010 ′bX100 ′b0100 ′b1000 ′b1000

[0071]FIG. 9 is a state transition diagram of the resource sharing statemachine 900 for controlling timing to process each request at one timein the resources sharing rake receiver structure 500. The resourcesharing state machine 900 generates a necessary timing by the channelpriority decision logic block 604 and the finger priority decision logicblock 606. If there is no request, the resource sharing state machine900 remains at an initial state (i.e., any WrPend!=1 and any RdPend!=1).If at least one pending signal exists (i.e., any WrPend==1 or anyRdPend==1), the resource sharing state machine 900 changes the initialstate into phase 1.

[0072] Here, the priority decision logic block 600 stores the presentlyselected channel, access type, and finger number in StCH, StRd, andStFng, respectively. Phase1 is automatically transitioned to phase2after one system clock, because two system clocks are required toprocess each request. If there is a pending signal, phase2 istransitioned to phase1 like the initial state. If there is no pendingsignal at phase1, the resource sharing state machine 900 sets channels,fingers, and operations to initial values and returns to the initialstate. Therefore, if there is a plurality of pending bits, one requestis processed and then the next request is sequentially processedaccording to a system clock.

[0073]FIG. 10 illustrates the structure of the acknowledgement signalgeneration logic block 1000. Upon simultaneous generation of a channelnumber, a finger number, and a phase1 signal stored in the resourcesharing state machine 900, the acknowledgement signal generation logicblock 1000 generates acknowledgement signals (WrAck or RdAck) andtransmits them to the corresponding pending status state machine 700,write pointer controller 610, and read pointer controller 612. Uponreceipt of the acknowledgement signals, the pending status state machine700 switches the corresponding pending bit into 0, and also the writepointer controller 610 and the read pointer controller 612 increase thewrite and read request pointers, respectively, of a correspondingchannel in a corresponding finger by 1.

[0074]FIG. 11 illustrates the timing of the first embodiment of thepresent invention where only the common time deskew buffer 314 is sharedin the case where 3 writing requests and 1 read request are generated.Once each request is generated, corresponding pending bits are switchedinto “1”, and are restored “0” in case of receipt of an acknowledgement.Here, the corresponding channels for processing are selected accordingto the priority scheme. Though the read requests are generated afterwrite requests, the read request is processed in advance because of itshigher priority over the write requests according to the priorityscheme.

[0075]FIG. 12 illustrates the timing of the second embodiment of thepresent invention where the common time deskew buffer 314 and phasecompensator 502 are shared in the case where 3 writing requests and 1read request are generated. In this case, phase3 is generated by 1 clockdelay with respect to phase2 in the resource sharing state machine 900,and phase 4 is generated by 1 clock delay with respect to phase3.However, as the phase3 and phase4 are overlaid to the phase1 and phase2of next request at temporal state, the required time for processing isable to keep two clocks. The operation of each phase in resource sharingstate machine 900 according to the sharing mode is shown in Table 4.TABLE 4 Operation according to the state of resource sharing statemachine Share both Time Deskew State of the Buffer and Phase CompensatorResource Sharing Share only Time Deskew Buffer Read State Machine WriteRequest Read Request Write Request Request Phase Initial — Read a storedOperation for — 1 path symbol phase Not Read a stored compensation (1)initial symbol path Phase Initial Store new Output after Operation for —2 path symbol Combining phase Not Combine the the stored compensation(2) initial stored symbol symbol with path with new scaling factorsymbol Phase Initial — — — Read a 3 path stored Not Read a stored symbolinitial symbol path Phase Initial — — Store new Output after 4 pathsymbol Combining Not Combine the the stored initial stored symbol symbolwith path with new scaling symbol factor

[0076] It will be understood that various modifications may be made tothe embodiments disclosed herein and that the above description shouldnot be construed as limiting, but merely as exemplifications ofpreferred embodiments. Accordingly, those skilled in the art willenvision other modifications within the scope and spirit of the claimsappended hereto.

What is claimed is:
 1. A rake receiver having a plurality ofdemodulating paths for demodulating symbols, the rake receivercomprising: a memory storage block for storing corresponding demodulatedsymbols from each of the plurality of demodulating paths; and storagecontrol circuitry connected to each of the plurality of demodulatingpaths for receiving the demodulated symbols and for controlling thestorage of the demodulated symbols within the memory storage block. 2.The rake receiver according to claim 1, further comprising readoutcontrol circuitry connected to the memory storage block for controllingthe reading out of the stored demodulated symbols.
 3. The rake receiveraccording to claim 1, further comprising a phase compensator connectedto the storage control circuitry for phase compensating the demodulatedsymbols corresponding to each of the plurality of demodulating pathsprior to storage of the demodulated symbols within the memory storageblock.
 4. A rake receiver having a plurality of demodulating paths fordemodulating symbols, the rake receiver comprising: storage controlcircuitry connected to each of the plurality of demodulating paths forreceiving the demodulated symbols; and a phase compensator connected tothe storage control circuitry for receiving the demodulated symbolscorresponding to each of the plurality of demodulating paths and forphase compensating the demodulated symbols.
 5. The rake receiveraccording to claim 4, further comprising a memory storage block forreceiving the phase compensated, demodulated symbols corresponding toeach of the plurality of demodulating paths and storing the demodulatedsymbols in accordance to signals received from the storage controlcircuitry.
 6. The rake receiver according to claim 5, further comprisingreadout control circuitry connected to the memory storage block forcontrolling the reading out of the stored demodulated symbols.
 7. A rakereceiver having a plurality of demodulating paths for demodulatingsymbols, the rake receiver comprising: a phase compensator for receivingthe demodulated symbols corresponding to each of the plurality ofdemodulating paths and for phase compensating the demodulated symbols;and a memory storage block for storing the phase compensated,demodulated symbols corresponding to each of the plurality ofdemodulating paths.
 8. A resource sharing rake receiver comprising: anantenna for receiving signals; a digital conversion block for convertingthe received signals to digital data; a plurality of demodulating pathsfor demodulating symbols within the digital data, wherein eachdemodulating path includes at least a PN despreading block, and a Walshdecovering block; a common memory storage block for storingcorresponding demodulated symbols from each of the plurality ofdemodulating paths; storage control circuitry connected to each of theplurality of demodulating paths for receiving the demodulated symbolsand for controlling the storage of the demodulated symbols within thecommon memory storage block according to write request signals receivedfrom each demodulating path; and readout control circuitry connected tothe common memory storage block for controlling the reading out of thestored demodulated symbols.
 9. The rake receiver according to claim 8,wherein the storage control circuitry includes a memory controller fordetermining whether one of a demodulated symbol and combined demodulatedsymbols stored in a memory location of the common memory storage blockshould be combined with a symbol processed by the storage controlcircuitry and stored at the same memory location.
 10. The rake receiveraccording to claim 9, wherein the memory controller determines whetherto combine one of the demodulated symbol and the combined demodulatedsymbols stored in the common memory storage block with the processedsymbol according to whether the processed symbol corresponds to a nextearliest demodulating path of the plurality of demodulating paths,wherein the next earliest demodulating path is the demodulating pathwhich outputs a next earliest demodulated symbol from among a series ofdemodulated symbols.
 11. The rake receiver according to claim 10,wherein the memory controller controls the combining of the processedsymbol with one of the demodulated symbol and the combined demodulatedsymbols stored in the common memory storage block by reading out one ofthe demodulated symbol and the combined demodulated symbols stored inthe common memory storage block upon receiving a read request signal,combining the read out symbol(s) with the processed symbol, and storingthe combined read out symbol(s) and the processed symbol at the samememory location.
 12. The rake receiver according to claim 8, wherein thestorage control circuitry includes a memory controller for controllingthe combining and storage of a series of demodulated symbols at the samememory location of the common memory storage block.
 13. The rakereceiver according to claim 12, wherein the memory controller stores afirst symbol of the series of demodulated symbols corresponding to anearliest demodulating path of the plurality of demodulating paths at thesame memory location of the common memory storage block, reads out thefirst symbol upon receiving a read request signal, combines the firstsymbol with a second symbol of the series of demodulated symbolscorresponding to a next earliest demodulating path of the plurality ofdemodulating paths, stores the combined first and second symbols at thesame memory location of the common memory storage block, and repeats theprocess until a last symbol of the series of demodulated symbols isreceived, such that the series of demodulated symbols are all combinedand stored at the same memory location of the common memory storageblock.
 14. The rake receiver according to claim 13, further comprisingmeans for numbering each of the plurality of demodulating paths, if twoor more demodulating paths are at the same position according to anarbitrary time period, for determining which of the two or moredemodulating paths is the earliest demodulating path.
 15. The rakereceiver according to claim 13, wherein the memory controller processesthe read request signal and the write request signals according to apriority scheme, and wherein only one read or write request signal canbe processed at any given time according to the priority scheme.
 16. Therake receiver according to claim 8, further comprising a prioritydecision block for determining the processing priority of the writerequest signals and sending at least one signal to the storage controlcircuitry indicative of the determined processing priority of the writerequest signals for storing symbols within the common memory storageblock.
 17. The rake receiver according to claim 16, wherein the prioritydecision block includes a reference timing generator (RTG) forgenerating read request signals, determining the processing priority ofthe read request signals, and sending at least one signal to the storagecontrol circuitry indicative of the determined processing priority ofthe read request signals for reading out symbols stored in the commonmemory storage block.
 18. The rake receiver according to claim 8,wherein the readout control circuitry comprises: a symbol combiner forreading out the stored demodulated symbols from the common memorystorage block and for combining the read out demodulated symbols; and along code descrambler for combining the combined demodulated symbolswith a long code.
 19. The rake receiver according to claim 18, whereinthe readout control circuitry further comprises a power bit extractorfor receiving the combined demodulated symbols from the symbol combinerand extracting the power bits.
 20. The rake receiver according to claim8, wherein each demodulating path further includes a channel estimationand phase compensation block for receiving output signals from arespective Walsh decovering block, phase compensating the symbols withinthe output signals, and sending the phase compensated, demodulatedsymbols to the common memory storage block.
 21. The rake receiveraccording to claim 8, further comprising a phase compensator blockconnected to the storage control circuitry for receiving the demodulatedsymbols corresponding to each of the plurality of demodulating paths andfor phase compensating the demodulated symbols prior to storing thedemodulated symbols within the common memory storage block.
 22. Aresource sharing rake receiver comprising: an antenna for receivingsignals; a digital conversion block for converting the received signalsto digital data; a plurality of demodulating paths for demodulatingsymbols within the digital data, wherein each demodulating path includesat least a PN despreading block, and a Walsh decovering block; a commonphase compensator block for receiving the demodulated symbolscorresponding to each of the plurality of demodulating paths and forphase compensating the demodulated symbols; a common memory storageblock for storing corresponding phase compensated, demodulated symbolsfrom each of the plurality of demodulating paths; storage controlcircuitry connected to each of the plurality of demodulating paths forreceiving the phase compensated, demodulated symbols and for controllingthe storage of the phase compensated, demodulated symbols within thecommon memory storage block according to write request signals receivedfrom each demodulating path; and readout control circuitry connected tothe common memory storage block for controlling the reading out of thestored phase compensated, demodulated symbols.
 23. The rake receiveraccording to claim 22, wherein the storage control circuitry includes amemory controller for determining whether one of a demodulated symboland combined demodulated symbols stored in a memory location of thecommon memory storage block should be combined with a symbol processedby the storage control circuitry and stored at the same memory location.24. The rake receiver according to claim 23, wherein the memorycontroller determines whether to combine one of the demodulated symboland the combined demodulated symbols stored in the common memory storageblock with the processed symbol according to whether the processedsymbol corresponds to a next earliest demodulating path of the pluralityof demodulating paths, wherein the next earliest demodulating path isthe demodulating path which outputs a next earliest demodulated symbolfrom among a series of demodulated symbols.
 25. The rake receiveraccording to claim 24, wherein the memory controller controls thecombining of the processed symbol with one of the demodulated symbol andthe combined demodulated symbols stored in the common memory storageblock by reading out one of the demodulated symbol and the combineddemodulated symbols stored in the common memory storage block uponreceiving a read request signal, combining the read out symbol(s) withthe processed symbol, and storing the combined read out symbol(s) andthe processed symbol at the same memory location.
 26. The rake receiveraccording to claim 22, wherein the storage control circuitry includes amemory controller for controlling the combining and storage of a seriesof demodulated symbols at the same memory location of the common memorystorage block.
 27. The rake receiver according to claim 26, wherein thememory controller stores a first symbol of the series of demodulatedsymbols corresponding to an earliest demodulating path of the pluralityof demodulating paths at the same memory location of the common memorystorage block, reads out the first symbol upon receiving a read requestsignal, combines the first symbol with a second symbol of the series ofdemodulated symbols corresponding to a next earliest demodulating pathof the plurality of demodulating paths, stores the combined first andsecond symbols at the same memory location of the common memory storageblock, and repeats the process until a last symbol of the series ofdemodulated symbols is received, such that the series of demodulatedsymbols are all combined and stored at the same memory location of thecommon memory storage block.
 28. The rake receiver according to claim27, further comprising means for numbering each of the plurality ofdemodulating paths, if two or more demodulating paths are at the sameposition according to an arbitrary time period, for determining which ofthe two or more demodulating paths is the earliest demodulating path.29. The rake receiver according to claim 27, wherein the memorycontroller processes the read request signal and the write requestsignals according to a priority scheme, and wherein only one read orwrite request signal can be processed at any given time according to thepriority scheme.
 30. The rake receiver according to claim 22, furthercomprising a priority decision block for determining the processingpriority of the write request signals and sending at least one signal tothe storage control circuitry indicative of the determined processingpriority of the write request signals for storing symbols within thecommon memory storage block.
 31. The rake receiver according to claim30, wherein the priority decision block includes a reference timinggenerator (RTG) for generating read request signals, determining theprocessing priority of the read request signals, and sending at leastone signal to the storage control circuitry indicative of the determinedprocessing priority of the read request signals for reading out symbolsstored in the common memory storage block.
 32. The rake receiveraccording to claim 31, wherein the priority decision block includes apending status state machine for receiving the write request and readrequest signals and registering the same according to their order ofgeneration by causing transition of a corresponding write pending orread pending bit, respectively, to a logic one value, and wherein eachwrite pending and read pending bit having a logic one value indicates apresently pending write or read request, respectively, to be processed.33. The rake receiver according to claim 32, wherein the prioritydecision block further includes a channel priority decision block and ademodulating path priority decision block for selecting a channel and ademodulating path from the plurality of demodulating paths,respectively, according to a priority scheme of the presently pendingwrite and read requests.
 34. The rake receiver according to claim 33,wherein the priority decision block further includes a resource sharingstate machine for receiving information about the selected channel anddemodulating path and sending signals to the storage control circuitryfor processing the presently pending write and read requests, andcontrolling the common memory storage block accordingly.
 35. The rakereceiver according to claim 34, wherein the priority decision blockfurther includes an acknowledgment signal generation logic block forreceiving the signals from the resource sharing state machine,generating at least one acknowledgment signal for at least the processedwrite and read requests corresponding to the presently pending write andread requests, and transmitting the at least one acknowledgment signalto the pending status state machine to indicate that the presentlypending write and read requests have been processed, and wherein uponreceipt of the at least one acknowledgment signal by the pending statusstate machine, the pending status state machine switches thecorresponding write and/or read pending bits to a logic zero value. 36.The rake receiver according to claim 35, wherein the at least oneacknowledgment signal is also transmitted to write and read pointercontroller blocks for increasing at least one corresponding writerequest pointer and at least one corresponding read request pointer,respectively, for processing a subsequent pending write and pending readrequest according to the priority scheme.
 37. The rake receiveraccording to claim 22, wherein the readout control circuitry comprises:a symbol combiner for reading out the stored demodulated symbols fromthe common memory storage block and for combining the read outdemodulated symbols; and a long code descrambler for combining thecombined demodulated symbols with a long code.
 38. The rake receiveraccording to claim 37, wherein the readout control circuitry furthercomprises a power bit extractor for receiving the combined demodulatedsymbols from the symbol combiner and extracting the power bits.
 39. Apriority decision block configured for a rake receiver, the prioritydecision block comprising: means for controlling the processing ofpending write and read requests for storing demodulated symbols to andreading out demodulated symbols from a memory storage block; and meansfor sending at least one signal to a memory controller for controllingthe storage and reading out of the demodulated symbols to and from thememory storage block in accordance with the processed pending write andread requests.
 40. The priority decision block according to claim 39,wherein the means for controlling the processing of pending write andread requests includes a pending status state machine for receivingwrite request and read request signals and registering the sameaccording to their order of generation by causing transition of acorresponding write pending or read pending bit, respectively, to alogic one value, and wherein each write pending and read pending bithaving a logic one value indicates one of the pending write and readrequests, respectively, to be processed.
 41. The priority decision blockaccording to claim 40, wherein the means for controlling the processingof pending write and read requests further includes a channel prioritydecision block and a demodulating path priority decision block forselecting a channel and a demodulating path from a plurality ofdemodulating paths of the rake receiver, respectively, according to apriority scheme of the pending write and read requests.
 42. The prioritydecision block according to claim 41, wherein the means for sending atleast one signal to the memory controller includes a resource sharingstate machine for receiving information about the selected channel anddemodulating path and sending signals to at least the memory controllerfor processing the pending write and read requests, and controlling thememory storage block accordingly.
 43. The priority decision blockaccording to claim 42, wherein the means for controlling the processingof pending write and read requests includes an acknowledgment signalgeneration logic block for receiving the signals from the resourcesharing state machine, generating at least one acknowledgment signal forat least the processed write and read requests corresponding to thepending write and read requests, and transmitting the at least oneacknowledgment signal to the pending status state machine to indicatethat the pending write and read requests have been processed, andwherein upon receipt of the at least one acknowledgment signal by thepending status state machine, the pending status state machine switchesthe corresponding write and/or read pending bits to a logic zero value.44. The priority decision block according to claim 43, furthercomprising write and read pointer controller block for receiving the atleast one acknowledgment signal for increasing at least onecorresponding write request pointer and at least one corresponding readrequest pointer, respectively, for processing a subsequent pending writeand pending read request of the pending write and read requestsaccording to the priority scheme.